Integrated circuits are widely used in electronic devices of many types. Conventional aluminum and aluminum alloys have been widely used as interconnection materials for integrated circuits. However, the downscaling of metal interconnect lines and the increase in electrical current density result in greater RC time delay along with enhanced electromigration and stress induced Vbid failures. To solve these functionality and reliability problems, an intense research effect has been focused on copper metalization due to its low bulk resistivity (1.68 μohm cm for Cu, compared to 2.7 μohm cm for Al), excellent electro-migration resistance, and high resistance to stress. However, copper metalization processes require a copper seed layer which is thin and has conformal step-coverage for eletroplating (ECP) or physical vapor deposition (PVD) trench-fill. The quality of the copper seed layer strongly affect the properties of the film that fills the trench, including crystalline quality, film adhesion strength, stress, and reliability within integrated circuits.
PVD Cu is known to be one of the best techniques for depositing a Cu seed layer due to its good physical step-coverage, good adhesion strength, particularly to diffusion barrier metal layer such as TiN, Ta and TaN. However, PVD Cu processes have been found to be less suitable when it becomes necessary to obtain uniform coverage of high aspect ratio trench and via side walls of the type seen in dual damascene structures. In this respect, Chemical Vapor Deposition (CVD) techniques have an advantage since they are able to achieve a high level of step-coverage (>80%).
CVD would therefore appear to be the technique of choice for Cu seed layer formation, particularly for next generation dual damascene technology. However, the Cu adhesion strength to the underneath layer (typically a diffusion barrier layer) is bad, it not being able even to pass the standard Scotch tape test. The grain structure of CVD Cu seed layers is another important factor. The surface roughness of CVD Cu seed layers may cause non uniform growth of subsequently deposited ECP Cu films, resulting in voids and incomplete gap filling. The texture of a CVD Cu seed also influences Cu interconnection failure induced by electromigration (EM) when applying higher current densities in ultra large scale integration circuits. It is well known that a <111> crystalline texture, including barrier layer and Cu film, brings improved Cu interconnections and increases EM endurance. However, CVD Cu seed layers tend to have a preferred <200> orientation rather than a <111> when deposited on some barrier materials.
Currently, PVD Cu remains the technique of choice for preparing Cu seed layers but CVD Cu processes are being considered for the next generation, because of its superior step coverage. The present invention discloses how CVD Cu may be used while at the same time, having good adhesion and a <111> preferred orientation.
A routine search of the prior art was performed with the following references of interest being found:
In US 2002-011,965,711 Gandikota et al. show a Cu process with a metal plasma CVD nucleation layer. In US 2002-0,068,449 A1 Hashim et al. disclose a Cu seed layer process with a metal plasma CVD nucleation layer while in U.S. Pat. No. 6,391,776 B2 Hashim et al. disclose a Cu seed layer process. Brown shows a Cu dual damascene process with a barrier layer in U.S. Pat. No. 6,306,732 B1.